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The 28th Asia and South Pacific Design Automation Conference

Session 7C  Security Assurance and Acceleration
Time: 10:20 - 11:35, Thursday, January 19, 2023
Location: Room Venus
Chairs: Prabhat Mishra (University of Florida, USA), Pengfei Qiu (Beijing University of Posts and Telecommunications, China)

7C-1 (Time: 10:20 - 10:45) (In-person)
TitleSHarPen: SoC Security Verification by Hardware Penetration Test
AuthorHasan Al-Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, *Mark Tehranipoor (University of Florida, USA)
Pagepp. 579 - 584
KeywordSoC Security Verification, Penetration Testing, Binary Particle Swarm, Cost Function, SoC Prototyping
AbstractAs modern SoC architectures incorporate many complex/heterogeneous intellectual properties (IPs), the protection of security assets has become imperative, and the number of vulnerabilities revealed is rising due to the increased number of attacks. Over the last few years, penetration testing (PT) has become an increasingly effective means of detecting software (SW) vulnerabilities. As of yet, no such technique has been applied to the detection of hardware vulnerabilities. This paper proposes a PT framework, SHarPen, for detecting hardware vulnerabilities, which facilitates the development of a SoC-level security verification framework. SHarPen proposes a formalism for performing gray-box hardware (HW) penetration testing instead of relying on coverage-based testing and provides an automation for mapping hardware vulnerabilities to logical/mathematical cost functions. SHarPen supports both simulation and FPGA-based prototyping, allowing us to automate security testing at different stages of the design process with high capabilities for identifying vulnerabilities in the targeted SoC.

7C-2 (Time: 10:45 - 11:10) (In-person)
TitleSecHLS: Enabling Security Awareness in High-Level Synthesis
AuthorShang Shi, Nitin Pundir, Hadi Mardani Kamali, Mark Tehranipoor, *Farimah Farahmandi (University of Florida, USA)
Pagepp. 585 - 590
KeywordHigh-Level Synthesis, Security, Scheduling, Binding
AbstractIn their quest for further optimization, High-level synthesis (HLS) utilizes advanced automatic optimization algorithms to achieve lower implementation time/effort for even more complex designs. These optimization algorithms are for the HLS tools’ backend stages, e.g., allocation, scheduling, and binding, and they are highly optimized for resources/latency constraints. However, current HLS tools’ backend is unaware of designs’ security assets, and their algorithms are incapable of handling security constraints. In this paper, we propose Secure-HLS (SecHLS), which aims to define underlying security constraints for HLS tools’ backend stages and intermediate representations. In SecHLS, we improve a set of widely-used scheduling and binding algorithms by integrating the proposed security-related constraints into them. We evaluate the effectiveness of SecHLS in terms of power, performance, area (PPA), security, and complexity (execution time) on small and real-size benchmarks, showing how the proposed security constraints can be integrated into HLS while maintaining low PPA/complexity burdens.

7C-3 (Time: 11:10 - 11:35) (In-person)
TitleA Flexible ASIC-oriented Design for a Full NTRU Accelerator
Author*Francesco Antognazza, Alessandro Barenghi, Gerardo Pelosi (Politecnico di Milano, Italy), Ruggero Susella (STMicroelectronics, Italy)
Pagepp. 591 - 597
KeywordPost Quantum Cryptography, Hardware Accelerator
AbstractPost-quantum cryptosystems are the subject of a significant research effort, witnessed by various international standardization competitions. Among them, the NTRU Key Encapsulation Mechanism has been recognized as a secure, patent-free, and efficient public key encryption scheme. In this work, we perform a design space exploration on an FPGA target, with the final goal of an efficient ASIC realization. Specifically, we focus on the possible choices for the design of polynomial multipliers with different memory bus widths to trade-off lower clock cycle counts with larger interconnections. Our design outperforms the best FPGA synthesis results at the state of the art, and we report the results of ASIC syntheses minimizing latency and area with a 40nm industrial grade technology library. Our speed-oriented design computes an encapsulation in 4.1 to 10.2 µs and a decapsulation in 7.1 to 11.7 µs, depending on the NTRU security level, while our most compact design only takes 20% more area than the underlying SHA-3 hash module.